Continued advances in the design of Random Access Memory devices (RAMs) has led to tremendous increases in their storage capacity. The storage capacity of individual RAMs has risen from 4K bits to 4 megabits within a relatively short time. In only a few years, 16-megabit RAMs are expected. The low cost of present-day RAMs now makes it practical to employ large arrays of such RAMs in computers and computer-based systems. When found in such computers and computer-based systems, such RAMs are arrayed on one or more printed wiring boards, usually called "memory boards."
As the storage capacity of present-day RAMs has increased, so too has the time required to test RAMs arrayed on memory boards by conventional testing techniques which typically involve software-based testing algorithms executed by a microprocessor. The simplest method of testing an array of RAMs is to write a first binary bit (e.g., a "1") into each successive storage location and then read the location to determine if the previously-written bit appears. Thereafter, a second binary bit (i.e., a "0") is written into each successive storage location and then a read operation is performed to see if indeed that bit now appears. (Whether a "1" or "0" is written first is immaterial.) If the bit read from a RAM location is different from the bit previously written into the same location, then a fault exists.
Algorithms for testing an array of RAMs by successively writing and reading "1"s and "0"s into successive locations are generally known as "marching" algorithms. The simplest marching algorithm is carried out by writing and reading a "1" into each successive RAM location followed by writing and then reading a "0" writing and then reading a "0" (or vice versa) into each such location. As may be appreciated, such a test requires accessing each memory location in each RAM in the array four separate times. For this reason, such a marching algorithm is said to have a complexity of 4N. More sophisticated marching algorithms, which require accessing each location more times, have a correspondingly greater complexity. Marching algorithms having a complexity of 14N or even 30N are not unusual.
The greater the number of times each storage location of each RAM in an array must be accessed, the longer the time for testing since there is a finite time (e.g., 80 nanoseconds) required to access each location. Even for a very fast microprocessor running at a speed as high as 33 MHz, the time required for the microprocessor to test a memory board having a large array of RAMs by executing a simple marching algorithm can be long.
Thus, there is a need for a circuit especially adapted for testing an array of RAMs in a rapid and efficient manner.